1. Field of the Invention
This invention relates to a data storage element and in particular to an emitter coupled logic (ECL) circuit having a fuse programmable latch/register bypass circuit.
2. Description of the Prior Art
Latch circuits are used generally as storage elements to store binary data received from an input data source. A latch is a logic function having an output that remains at a particular logic level after it has been forced to that state by an external signal. The latch output remains at that level even though the external signal that forced the latch to its state is no longer present. A clocked latch is a latch circuit having a state that is only changeable when a clock signal is in a given state, and the latch retains its current state until the clock signal changes polarity and allows entry to a new state. Two clocked latch circuits may be configured as master and slave sections connected in series, with the clock input of the slave section being the complement of the clock applied to the master section to form a clocked register. In prior art logic circuits, the data output of the latch circuit is dependent upon the clock input signal.
It would be desirable to utilize a latch circuit but to change its function so that it acts merely as a buffer and does not latch, even upon the application of clock signals of both states, i.e., high or low, whereby the output signal is a combinatorial signal as opposed to a clocked signal. Thus, the combinatorial signal is always a direct function of the current data input signal.